The present invention relates to a semiconductor device.
With the high integration and miniaturization of semiconductor devices, there is an increasing trend in which a plurality of fine elements, which form a semiconductor device, are multi-layered so as to overlap each other, when viewed from above. With the multi-layering of the semiconductor devices, a technique for electrically coupling, by a coupling layer referred to as a plug, a source/drain region of a transistor formed over the major surface of a semiconductor substrate to a layer located over the transistor is frequently used. Structures, in each of which a source/drain region of a transistor and a layer arranged over the transistor are electrically coupled to each other by a plug conductive layer, are disclosed in, for example, Japanese Unexamined Patent Publication No. 2004-79696 and Japanese Unexamined Patent Publication No. 2003-332464, etc.
The semiconductor device disclosed in Japanese Unexamined Patent Publication No. 2004-79696 is a volatile memory referred to as an SRAM (Static Random Access Memory). In the SRAM disclosed therein, a capacitor as a so-called DRAM (Dynamic Random Access Memory) is added to an SRAM circuit in which a thin film transistor, referred to as a so-called TFT (Thin Film Transistor), is used as a load transistor. A charge is held in the capacitor, instead of a memory node, and an electric potential in the capacitor is held by a so-called flip-flop circuit that forms the SRAM circuit. Accordingly, occurrence of a soft error, due to an alpha ray (α ray), can be suppressed in comparison with an SRAM in which a charge is accumulated in a memory node. Further, at least part of the flip-flop circuit is provided over a bit-line, and hence the semiconductor device can be made small (miniaturized).
In Japanese Unexamined Patent Publication No. 2003-332464, an eave-shaped lead-out portion that only contacts the side of a contact electrode is formed.